A dynamic random access memory (DRAM) cell typically includes a charge storage capacitor coupled to an access device such as a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). The MOSFET functions to apply or remove charge on the capacitor, thus affecting a logical state defined by the stored charge. The conditions of DRAM operation, such as operating voltage, leakage rate and refresh rate, will, in general, mandate that a certain minimum charge be stored by the capacitor.
In the continuing trend to higher memory capacity, the packing density of storage cells must increase, yet each must maintain required capacitance levels. This is a crucial demand of DRAM fabrication technologies if future generations of expanded memory array devices are to be successfully manufactured. Nevertheless, in the trend to higher memory capacity, the packing density of cell capacitors has increased at the expense of available cell area. For example, the area allowed for a single cell in a 64-Mbit DRAM is only about 1.4 μm2. In such limited areas, it is difficult to provide sufficient capacitance using conventional stacked capacitor structures. As a result, features of the DRAM cell may be formed with high aspect ratios (i.e., the ratio of height to width). These high aspect ratios can decrease the stability of such features causing the features to wobble or wave and may damage the cell.
Similarly, as the size of storage cells decreases, interconnects, such as bit lines and wordlines, may decrease in size, e.g., width, while also being relied upon to provide support to the features in the storage cell.
Accordingly, there is a need for a method of forming an MIM capacitor having increased stability and strength without increasing the size of the MIM capacitor, as well as a method of forming an interconnect and a wordline with increased strength to add support to components of a memory cell.